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Volumn 47, Issue 2 I, 2000, Pages 362-366
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Pattern recognition algorithms on FPGAs and CPUs for the ATLAS LVL2 trigger
a a a a a a a |
Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
COMPUTER ARCHITECTURE;
DATA PROCESSING;
FEATURE EXTRACTION;
FIELD PROGRAMMABLE GATE ARRAYS;
PERSONAL COMPUTERS;
TRACK RECONSTRUCTION;
TRIGGER ALGORITHMS;
PARTICLE DETECTORS;
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EID: 0033690788
PISSN: 00189499
EISSN: None
Source Type: Journal
DOI: 10.1109/23.846182 Document Type: Article |
Times cited : (5)
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References (10)
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