Speeding up hardware prototyping by incremental simulation/emulation

Proceedings of the International Workshop on Rapid System Prototyping

Volumn , Issue , 2000, Pages 98-102

  Canellas N ^a   Moreno, J M ^b  

^a UNIVERSITAT ROVIRA I VIRGILI   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION;

LOGIC EMULATORS; TEXT FILES;

RAPID PROTOTYPING;

EID: 0033688886     PISSN: 10746005     EISSN: None     Source Type: Journal    
DOI: 10.1109/IWRSP.2000.855203     Document Type: Article

References (7)

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4. R. Tessier Incremental Compilation for Logic Emulation Proceedings of the 10 International Workshop on Rapid System Prototyping Proceedings of the 10 International Workshop on Rapid System Prototyping 1999
5. J. D. Sterling A. Dollas Extended VHDL for the Rapid Prototyping of Systems With Synthesizable and Nonsynthesizable Subsystems Proceedings of the 5 International Workshop on Rapid System Prototyping Proceedings of the 5 International Workshop on Rapid System Prototyping 1994
6. IEEE Standard VHDL Language Reference Manual IEEE Std1076-1993
7. J. Faura J. M. Moreno M. A. Aguirre P. van Duong J. M. Insenser Multicontext Dynamic Reconfiguration and Real Time Probing on a Novell Mixed Signal Programmable Device With On-Chip Microprocessor Proceedings of Field Programmable Logic and Applications Proceedings of Field Programmable Logic and Applications 1997