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Volumn 4019, Issue , 2000, Pages 315-323

Residual thermo-mechanical stresses in ultra thin chip stack technology

Author keywords

[No Author keywords available]

Indexed keywords

BUTENES; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LIGHT SENSITIVE MATERIALS; MATHEMATICAL MODELS; MULTICHIP MODULES; OPTIMIZATION; RESIDUAL STRESSES; STRESS ANALYSIS; THERMAL STRESS;

EID: 0033688416     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (14)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.