Pulse mode multilayer neural network with floating point operation and on-chip learning

Proceedings of the International Joint Conference on Neural Networks

Volumn 2, Issue , 2000, Pages 71-76

  Hikawa, Hiroomi ^a  

^a OITA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BACKPROPAGATION; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS; LEARNING ALGORITHMS; LEARNING SYSTEMS;

FLOATING POINT NUMBER SYSTEM;

MULTILAYER NEURAL NETWORKS;

EID: 0033685669     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ijcnn.2000.857877     Document Type: Conference Paper

References (6)