Programmable VLSI architecture for 2-D discrete wavelet transform

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2000, Pages

  Chen, Chien Yu ^a   Yang, Zhong Lan ^a   Wang, Tu Chih ^a   Chen, Liang Gee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; IMAGE ANALYSIS; IMAGE QUALITY; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; STANDARDS; WAVELET TRANSFORMS;

DISCRETE WAVELET TRANSFORMS (DWT); JOINT PICTURE EXPERTS GROUP (JPEG) STANDARDS;

VLSI CIRCUITS;

EID: 0033684051     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.857171     Document Type: Conference Paper

References (7)