Methodology for MOS transistor mismatch parameter extraction and mismatch simulation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2000, Pages

  Serrano Gotarredona, T ^a   Linares Barranco, B ^a  

^a Natl Microelectronics Cent   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; PARAMETER ESTIMATION;

MISMATCH PARAMETER EXTRACTION; SOFTWARE PACKAGE HSPICE;

MOSFET DEVICES;

EID: 0033683735     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.858700     Document Type: Conference Paper

References (6)