Simple built-in self test for dual ported SRAMs

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 2000, Pages 79-84

  Truong, Khoan ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDRESS SCRAMBLING SCHEME; DUAL PORTED STATIC RANDOM ACCESS MEMORY; MARCH TEST;

ALGORITHMS; COST BENEFIT ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; RANDOM ACCESS STORAGE;

BUILT-IN SELF TEST;

EID: 0033682575     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)