|
Volumn , Issue , 2000, Pages 250-252
|
Power-optimal encoding for DRAM address bus
|
Author keywords
[No Author keywords available]
|
Indexed keywords
CENTRAL PROCESSING UNITS (CPU);
EULERIAN CYCLE;
PYRAMID CODE;
CODES (SYMBOLS);
GRAPH THEORY;
MATHEMATICAL MODELS;
DYNAMIC RANDOM ACCESS STORAGE;
|
EID: 0033666676
PISSN: 15334678
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (9)
|
References (9)
|