Noise-aware power optimization for on-chip interconnect

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2000, Pages 108-113

  Kim, Ki Wook ^a   Jung, Seong Ook ^a   Narayanan, Unni ^a   Liu, C L ^a   Kang, Sung Mo ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; FORMAL LOGIC; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE; SWITCHING;

CROSS-COUPLING; CYCLE-AVERAGED POWER MODEL;

INTERCONNECTION NETWORKS;

EID: 0033651719     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (14)