Overview of Cu contamination during integration in a dual damascene architecture for sub-quarter micron technology

Microelectronic Engineering

Volumn 50, Issue 1-4, 2000, Pages 425-431

  Torres, J ^a   Palleau, J ^a   Tardif, F ^b   Bernard, H ^c   Beverina, A ^c   Motte, P ^c   Pantel, R ^a   Juhel, M ^a  

^a ORANGE LABS   (France)

^b CEA LETI   (France)

^c STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL CLEANING; CHEMICAL POLISHING; CONTAMINATION; ETCHING; LEAKAGE CURRENTS; METALLIZING;

CHEMICAL MECHANICAL POLISHING (CMP); DUAL DAMASCENE ARCHITECTURE;

COPPER;

EID: 0033640273     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(99)00311-1     Document Type: Article

References (4)

1. Gravier T., Braud F., Torres J., Palleau J., Chantre A., Kirtsch J. Proceedings of VMIC Santa Clara. 1996;327.
2. Dubin V.M., Adem E.H., Bernard J., Schonauer D., Bertrand J. Proceedings of Advanced Metalization and Interconnect Systems for ULSI Applications in 1996. MRS :1997;421.
3. Tardif F., Palleau J., Lardin T., Demolliens O., Vincent A., Torres J. Microelectronic Engineering. 33:1997;195.
4. Ueno K., Donnelly V.M., Kikkawa T. J. Electrochem. Soc. 144:(7):1997;2565.