Selective CMP process for stacked low-k CVD oxide films

Microelectronic Engineering

Volumn 50, Issue 1-4, 2000, Pages 53-58

  Hartmannsgruber, E ^a   Zwicker, G ^a   Beekmann, K ^b  

^a FRAUNHOFER INSTITUTE FOR SILICON TECHNOLOGY ISIT   (Germany)

^b Trikon Technologies Ltd   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL POLISHING; CHEMICAL VAPOR DEPOSITION; DIELECTRIC FILMS; PERMITTIVITY; SILICA; THIN FILMS;

CHEMICAL MECHANICAL POLISHING (CMP); DIELECTRIC PLANARIZATION; REMOVAL RATE SELECTIVITY;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0033640228     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(99)00264-6     Document Type: Article

References (5)

1. Dobson C., Kiermasz A., Beekmann K., Wilby R. Semiconductor International, Dec. 1994.
2. McClatchie S., Beekmann K., Kiermasz A. Proc. DUMIC, Feb. 16-17 :1998.
3. Matsuura M., Tottori I., Goto K., Maekawa K., Mashiko Y., Hirayama M. IEDM Conference, Dec. 7-10 :1997.
4. Hartmannsgruber E., Kulawski M., Zwicker G., Beekmann K. Proc. VMIC, June 16-18 :1998.
5. Burke P., Witt K. Proc. Implementation and Improvements of Chemical Mechanical Polishing (CMP) Process, SEMICON Europa 97 Technical Programs, April 17th :1997.