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Volumn , Issue , 1999, Pages 306-307

A virtual logic algorithm for solving satisfiability problems using reconfigurable hardware

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; C (PROGRAMMING LANGUAGE); COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; COMPUTER HARDWARE; COMPUTER SOFTWARE;

EID: 0033488516     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (2)

References (15)
  • 1
    • 0032630145 scopus 로고    scopus 로고
    • A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
    • M. Abramovici, J. Sousa, and D. Saab, "A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware," submitted to Design Automation Conf., 1999
    • (1999) Design Automation Conf.
    • Abramovici, M.1    Sousa, J.2    Saab, D.3
  • 5
    • 0024926609 scopus 로고
    • Optimal layout via boolean satisfiability
    • November
    • S. Devadas, "Optimal Layout Via Boolean Satisfiability," Proc. Intn'l. Conf. on CAD, pp. 294-297, November 1989
    • (1989) Proc. Intn'l. Conf. on CAD , pp. 294-297
    • Devadas, S.1
  • 6
    • 0026981958 scopus 로고
    • Certified timing verification and the transition delay of a logic circuit
    • June
    • S. Devadas, K. Keutzer, S. Malik, and A. Wang, "Certified Timing Verification and the Transition Delay of a Logic Circuit," Proc. Design Automation Conf., pp. 549-555, June, 1992
    • (1992) Proc. Design Automation Conf. , pp. 549-555
    • Devadas, S.1    Keutzer, K.2    Malik, S.3    Wang, A.4
  • 7
    • 0012167824 scopus 로고    scopus 로고
    • DIMACS Challenge Benchmarks
    • DIMACS Challenge Benchmarks, ftp://dimacs.rutgers.edu/pub/challenge/sat/benchmarks/cnf/
  • 8
    • 0026623575 scopus 로고
    • Test pattern generation using boolean satisfiability
    • January
    • T. Larrabee, "Test Pattern Generation Using Boolean Satisfiability," IEEE Trans. on CAD, Vol. 11, No. 1, pp. 4-15, January, 1992
    • (1992) IEEE Trans. on CAD , vol.11 , Issue.1 , pp. 4-15
    • Larrabee, T.1
  • 9
    • 0027061384 scopus 로고
    • Timing analysis and delay-fault test generation using path recursive functions
    • November
    • P. C. McGeer et al., "Timing Analysis and Delay-Fault Test Generation Using Path Recursive Functions," Proc. Intn'l. Conf. on CAD, pp. 180-183, November 1991
    • (1991) Proc. Intn'l. Conf. on CAD , pp. 180-183
    • McGeer, P.C.1
  • 14
    • 0030389116 scopus 로고    scopus 로고
    • BIST fault diagnosis in scan-based VLSI environments
    • October
    • Y. Wu and S. Adham, "BIST Fault Diagnosis in Scan-Based VLSI Environments," Proc. Intn'l. Test Conf., pp. 48-57, October 1996
    • (1996) Proc. Intn'l. Test Conf. , pp. 48-57
    • Wu, Y.1    Adham, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.