Reducing compilation time of Zhong's FPGA-based SAT solver

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1999, Pages 308-309

  Chan, Pak K ^a   Boyd, M J ^a   Goren, S ^a   Klenk, K ^a   Kodavati, V ^a   Kundu, R ^a   Margolese, M ^a   Sun, J ^a   Suzuki, K ^a   Thorne, E ^a   Wang, X ^a   Xu, J ^a   Zhu, M ^a  

^a University of California Santa Cruz   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; FINITE AUTOMATA; MICROPROCESSOR CHIPS; PRINTED CIRCUIT BOARDS;

BOARD-LEVEL MULTIPLE-CHIP ARCHITECTURE; FINITE STATE MACHINES; SATISFIABILITY SOLVER;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0033488481     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)