Test structures for MCM-D technology characterization

IEEE Transactions on Semiconductor Manufacturing

Volumn 12, Issue 2, 1999, Pages 184-192

  Lozano, Manuel ^a,b   Santander, Joaquín ^b   Cabruja, Enric ^b   Perelló, Carles ^c   Ullán, Miguel ^b   Lora Tamayo, Emilio ^b   Doyle, Rory ^d   McCarthy, Ger ^d   Barton, John ^d  

^a IEEE

^b UNIVERSITAT AUTÒNOMA DE BARCELONA   (Spain)

^c IMEC   (Belgium)

^d UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; ELECTRONICS PACKAGING; FLIP CHIP DEVICES; INTEGRATED CIRCUIT LAYOUT; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE TESTING; SILICON WAFERS; THERMAL EXPANSION; YIELD STRESS;

CONTACT RESISTANCE; SILICON SUBSTRATE TECHNOLOGY; TEST STRUCTURES;

MULTICHIP MODULES;

EID: 0033363407     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.762876     Document Type: Article

References (13)

1. J. W. Balde, Multichip Modules, Systems Advantages, Major Constructions and Materials Technologies. New York: IEEE Press, 1991.
2. P. Garrou, "Polymer dielectric for multichip module packaging," Proc. IEEE, vol. 80, pp. 1942-1954, Dec. 1992.
3. J. H. Lau, Chip on board Technologies for Multichip Modules. New York: Van Nostrand Reinhold, 1995.
4. M. Lozano, J. Santander, E. Cabruja, C. Perelló, and E. Lora-Tamayo, "Test structures for MCM-D technology characterization," in IEEE Int. Conf. Microelectronic Test Structures, Kanazawa, Japan, 1998, pp. 183-188.
5. C. Perelló and J. Santander, "Test structures on the substrate A and F (mask set CNM071 and CNM075) for project SUMMIT," Tech. Rep. 100/97, Microelectronics National Center (CNM), Barcelona, Spain, Jan. 1997.
6. M. G. Buehler and W. R. Thurber, "An experimental study of various cross sheet resistor test structures," J. Electrochem. Soc., vol. 125, no. 4, pp. 645-650, Apr. 1978.
7. M. G. Buehler, S. D. Grant, and W. R. Thurber, "Bridge and Van der Pauw sheet resistors for characterizing the line width of conducting layers," J. Electrochem. Soc., vol. 125, no. 4, pp. 650-654, Apr. 1978.
8. S. S. Cohen and G. Sh. Gildenblat, Metal-Semiconductor Contacts and Devices, vol. 13 of VLSI Electronics: Microstructure Science, chapter Test structures for ohmic contact characterization. New York: Academic, 1986.
9. A. Scorzoni and M. Finetti, "Metal/semiconductor contact resistivity and its determination from contact resistance measurements," Mat. Sci. Rep., vol. 3, no. 2, pp. 79-138, 1988.
10. D. J. Radack, C. T. Yao, L. W. Linholm, K. F. Galloway, and H. C. Lin, "Comparison of microelectronic test structures for propagation delay measurements," Microelectron. J., vol. 16, no. 6, pp. 39-46, June 1985.
11. S. Long, "Test structures for timing measurements," in Proc. Test Chip Workshop, Pasadena, CA, USA, 1983, pp. 11-25.
12. J. Santander, M. Lozano, A. Götz, C. Cané, and E. Lora-Tamayo, "Universal surfaces for the accurate contact resistivity extraction on Kelvin structures with upper and lower resistive layers," in IEEE Int. Conf. Microelectronic Test Structures, Trento, Italy, 1996, pp. 67-74.
13. S. C. O'Mathuna, "Test chips, test systems and thermal test data for multi-chip modules in the ESPRIT-APACHIP project," IEEE Trans. Comp., Packag., Manufact. Technol. A, vol. 17, Sept. 1994.