Power minimization of high-performance submicron CMOS circuits using a dual-Vdd dual-Vth (DVDV) approach

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 106-108

  Khellah, Muhammad M ^a   Elmasry, M I ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); HEURISTIC METHODS; LEAKAGE CURRENTS; LOGIC DESIGN; THRESHOLD VOLTAGE;

DEPTH-FIRST-SEARCH (DFS) BASED HEURISTICS;

LOGIC CIRCUITS;

EID: 0033362678     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/313817.313881     Document Type: Article

References (4)