Lower bounding techniques for the multiprocessor scheduling problem with communication delay

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 1999, Pages 212-220

  Fujita, Satoshi ^a   Nakagawa, Tadanori ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; RANDOM PROCESSES; RESPONSE TIME (COMPUTER SYSTEMS);

INEVITABLE COMMUNICATION DELAY; MULTIPROCESSOR SCHEDULING PROBLEMS (MSP);

PARALLEL PROCESSING SYSTEMS;

EID: 0033362480     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (10)