Efficient and safe asynchronous wave-pipeline architectures for datapath and control unit applications

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1999, Pages 38-41

  Hauck, O ^a   Garg, M ^a   Huss, S A ^a  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER SIMULATION; DATA FLOW ANALYSIS; FEEDBACK; NETWORK PROTOCOLS; TRIGGER CIRCUITS;

ASYNCHRONOUS WAVE PIPELINE ARCHITECTURE; DATAPATH; DOUBLE PASS TRANSISTOR LOGIC;

PIPELINE PROCESSING SYSTEMS;

EID: 0033361427     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)