Noise immunity of digital circuits in mixed-signal smart power systems

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1999, Pages 314-317

  Secareanu, Radu M ^a   Kourtev, Ivan S ^a   Becerra, Juan ^a   Watrobski, Thomas E ^a   Morton, Christopher ^a   Staub, William ^a   Tellier, Thomas ^a   Friedman, Eby G ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE; SUBSTRATES;

DIGITAL LATCHES; MIXED SIGNAL SMART POWER SYSTEMS; NMOS PROCESS; NOISE IMMUNITY;

POWER SUPPLY CIRCUITS;

EID: 0033361397     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)