PASTA: partial scan to enhance test compaction

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1999, Pages 4-7

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; HEURISTIC METHODS; LOGIC DESIGN;

FAULT COVERAGE; PARTIAL SCAN; TEST COMPACTION; TEST LENGTH;

INTEGRATED CIRCUIT TESTING;

EID: 0033361291     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)