Design of fault-tolerant solid state mass memory

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1999, Pages 302-310

  Cardarilli, G C ^a   Marinucci, P ^a   Bertazzoni, S ^a   Salmeri, M ^a   Salsano, A ^a  

^a UNIVERSITY OF ROME TOR VERGATA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; CONSTRAINT THEORY; ERROR ANALYSIS; ERROR CORRECTION; FAULT TOLERANT COMPUTER SYSTEMS;

COMMERCIAL OFF THE SHELF DYNAMIC RANDOM ACCESS MEMORY (COTS DRAM); ERROR CORRECTING CODES (ECC); FAULT TOLERANT SOLID STATE MASS MEMORY (SSMM);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0033356634     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)