Efficient implementation of rounding units

Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers

Volumn 2, Issue , 1999, Pages 1489-1493

  Burgess, N ^a   Knowles, S ^b  

^a CARDIFF UNIVERSITY   (United Kingdom)

^b Aztec West ^*  (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDITIONAL LOGIC; CARRY PROPAGATE ADDITION; EFFICIENT IMPLEMENTATION; FLOATING POINT STANDARDS; IEEE-754; PARALLEL PREFIX ADDER; ROUNDING MODES;

DIGITAL ARITHMETIC; COMPUTATION THEORY;

ADDERS; DIGITAL ARITHMETIC; MULTIPLYING CIRCUITS;

FLAGGED PREFIX ADDER; ROUNDING OPERATIONS;

EID: 0033352554     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.1999.831998     Document Type: Conference Paper

References (9)

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3. R.K. Yu and G.B. Zyner, "167 MHz floating-point multiplier", Proc. 12th IEEE Symp. Computer Arithmetic, Bath, pp. 149-154, July 1995
4. M.J. Flynn et 01, "The SNAP project: Towards subnanosecond arithmetic", Proc. 12th IEEE Symp. Computer Arithmetic, pp. 75-82, Bath, July 1995
5. M.R. Santoro, G. Bewick and M.A. Horowitz, (1989) "Rounding Algorithms for IEEE Multipliers", Proc. 9th IEEE Symp. Computer Arithmetic, pp. 176-183, Santa Monica, September 1989
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8. R.E. Ladner and M.J. Fischer "Parallel prefix computation", J. ACM, vol. 27, pp. 831-838, May 1980
9. S.C. Knowles, "Simultaneous Arithmetic", British Patent Application, June 1998