|
Volumn 3, Issue , 1999, Pages 1775-1779
|
Analysis and measurement of chip current imbalances caused by the structure of bus bars in an IGBT module
a a a a a |
Author keywords
[No Author keywords available]
|
Indexed keywords
CHIP CURRENT IMBALANCES;
INSULATED GATE BIPOLAR TRANSISTORS MODULE;
PARALLEL CIRCUITS;
TEST MODULE;
BIPOLAR TRANSISTORS;
COMPUTER SIMULATION;
ELECTRIC CURRENTS;
ELECTRIC NETWORK TOPOLOGY;
FINITE ELEMENT METHOD;
MAXWELL EQUATIONS;
MULTICHIP MODULES;
SEMICONDUCTOR DEVICE MODELS;
THREE DIMENSIONAL;
BUSBARS;
|
EID: 0033351924
PISSN: 01972618
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (16)
|
References (3)
|