Fault-tolerant refresh power reduction of DRAMs for quasi-nonvolatile data retention

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1999, Pages 311-318

  Katayama, Yasunao ^a   Stuckey, Eric J ^a   Morioka, Sumio ^a   Wu, Zhao ^a  

^a Tokyo Research Laboratories   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); DATA RECORDING; DATA REDUCTION; ERROR CORRECTION; FAULT TOLERANT COMPUTER SYSTEMS; NONVOLATILE STORAGE; POWER CONTROL; SENSITIVITY ANALYSIS;

QUASI-NONVOLATILE MEMORY SYSTEMS; REED-SOLOMON ERROR CORRECTING CODE (ECC);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0033350065     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)