Threshold voltage design incompatibility between partially-depleted SOI and bulk CMOS transistors

IEEE International SOI Conference

Volumn , Issue , 1999, Pages 32-33

  van Meer, Hans ^a   Lyu, Jeong Ho ^a   Kubicek, Stefan ^a   Geenen, Luc ^a   De Meyer, Kristin ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTERFACES (MATERIALS); MOSFET DEVICES; SILICA; SILICON WAFERS; THRESHOLD VOLTAGE;

FULLY-DEPLETED SILICON ON INSULATOR (FD SOI) TECHNOLOGY; PARTIALLY-DEPLETED SILICON ON INSULATOR (PD SOI) TECHNOLOGY;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0033348729     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)