Method to optimize gate oxide integrity, hot carrier effect and electro-static discharge without sacrificing the performance in sub-quarter micron dual gate oxide process

Japanese Journal of Applied Physics, Part 2: Letters

Volumn 38, Issue 11 B, 1999, Pages

  Shih, Jiaw Ren ^a   Lee, Jian Hsing ^a   Chen, Shui Hung ^a   Wu, Yi Hsun ^a   Diaz, Carlos H ^a   Liew, Boon Khim ^a   Hwang, Huey Liang ^b  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC; ELECTRIC DISCHARGES; ELECTROSTATICS; HOT CARRIERS; INTEGRATED CIRCUITS; ION IMPLANTATION; OXIDES; PHOSPHORUS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING;

ELECTROSTATIC DISCHARGES; GATE OXIDES; LIGHTLY DOPED DRAIN (LDD) STRUCTURE; SUB-QUARTER MICRON DUAL GATE OXIDE PROCESS;

GATES (TRANSISTOR);

EID: 0033344572     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.38.l1287     Document Type: Article

References (5)

1. N. Bhat, P. Chen, P. Tsui, A. Das, M. Foisy, Y. Shino, J. Higman, J. Nguyen, S. Gonzales, S. Collins and D. Workman: IEEE IEDM Tech. Dig., 1998, p. 931.
2. C. H. Diaz, C. H. Wang, C. C. Wud, S. H. Chend, B. L. Lina, B. K. Liew, K. L. Yang and J. Y.-C. Sun: IEEE VLSI Symp., 1999, p. 37.
3. J.-R. Shih and S. H. Liaw: United States Patent 572352 (1998).
4. F.-C. Hsu et al: IEEE EDL-5 (1984) 71.
5. J.-R. Shih, J.-H. Lee, H.-L. Hwang, B.-K. Liew and S. Y. Chiang: Jpn. J. Appl. Phys. 38 (1999) 4632.