Scalable low-complexity digit-serial VLSI architecture for RSA cryptosystem

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 1999, Pages 586-595

  Leu, Jye Jong ^a   Wu, An Yeu ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; CRYPTOGRAPHY; INTEGRATED CIRCUIT LAYOUT; PIPELINE PROCESSING SYSTEMS; VLSI CIRCUITS;

BOOTH-ENCODED MONTGOMERY MODULAR MULTIPLICATION ALGORITHM;

SIGNAL ENCODING;

EID: 0033343160     PISSN: 15206130     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)