80 nm dual-gate CMOS with shallow extensions formed after activation annealing and SALICIDE

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1999, Pages 649-652

  Morifuji, E ^a   Ohishi, A ^a   Miyashita, K ^a   Kawashima, H ^a   Nakayama, T ^a   Yoshimura, H ^a   Toyoshima, Y ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; DEPOSITION; GATES (TRANSISTOR); NITRIDES; OXIDATION; RELIABILITY; SEMICONDUCTING FILMS; SEMICONDUCTING SILICON COMPOUNDS; TEMPERATURE; THERMAL DIFFUSION IN SOLIDS; THERMAL EFFECTS;

ACTIVATION ANNEALING; NITRIDE COVER FILM; SHALLOW EXTENSIONS FORMED AFTER ACTIVATION ANNEALING; SILICIDE;

CMOS INTEGRATED CIRCUITS;

EID: 0033339639     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)