Formal specification and verification of a dataflow processor array

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 494-499

  Henzinger, Thomas A ^a   Liu, Xiaojun ^a   Qadeer, Shaz ^a   Rajamani, Sriram K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; DATA COMMUNICATION SYSTEMS; DATA FLOW ANALYSIS; DATA TRANSFER; DIGITAL SIGNAL PROCESSING; FORMAL LOGIC; IMAGE PROCESSING; PIPELINE PROCESSING SYSTEMS; QUEUEING THEORY; WORLD WIDE WEB;

DATAFLOW PROCESSOR ARRAY; MOCHA; VGI CHIP;

PARALLEL PROCESSING SYSTEMS;

EID: 0033337609     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)