Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies

IEEE International Test Conference (TC)

Volumn , Issue , 1999, Pages 1031-1037

  Dworak, Jennifer ^a   Grimaila, Michael R ^a   Lee, Sooryong ^a   Wang, Li C ^a   Mercer, M Ray ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED SOFTWARE ENGINEERING; DIGITAL INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; NAND CIRCUITS; PROBABILITY; SEMICONDUCTOR DEVICE MODELS;

AUTOMATIC TEST PATTERN GENERATION; DEFECT EXCITATION; DEFECTIVE PART LEVEL;

INTEGRATED CIRCUIT TESTING;

EID: 0033336286     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)