Testability evaluation of sequential designs incorporating the multi-mode scannable memory element

IEEE International Test Conference (TC)

Volumn , Issue , 1999, Pages 286-293

  Singh, Adit D ^a   Sogomonyan, Egor S ^a   Gossel, Michael ^a   Seuring, Markus ^a  

^a AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; SEQUENTIAL CIRCUITS;

CIRCULAR SELF TEST PATH; MULTIMODE SCANNABLE MEMORY ELEMENT;

DESIGN FOR TESTABILITY;

EID: 0033332916     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)