Collision detection VLSI processor for intelligent vehicles using a hierarchically-content-addressable memory

IEICE Transactions on Electronics

Volumn E82-C, Issue 9, 1999, Pages 1722-1729

  Hariyama, Masanori ^a   Sasaki, Kazuhiro ^a   Kameyama, Michitaka ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Area time product minimization; CAM; Hierarchical collision detection; Path planning

Indexed keywords

ALGORITHMS; ASSOCIATIVE STORAGE; COLLISION AVOIDANCE; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL GEOMETRY; HIERARCHICAL SYSTEMS; INTELLIGENT VEHICLE HIGHWAY SYSTEMS; MATHEMATICAL TRANSFORMATIONS; MATRIX ALGEBRA; MOTION PLANNING; OPTIMIZATION; VLSI CIRCUITS;

AREA TIME PRODUCT MINIMIZATION; HIERARCHICAL COLLISION DETECTION; HIERARCHICALLY CONTENT ADDRESSABLE MEMORY; HIERARCHICALLY MATCHING;

MICROPROCESSOR CHIPS;

EID: 0033331151     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

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