Modeling yield throughout the DRAM product life cycle

1999 IEEE International Symposium on Semiconductor Manufacturing, ISSM 1999 - Conference Proceedings

Volumn , Issue , 1999, Pages 123-126

  Simmons, S ^a  

^a MICRON TECHNOLOGY INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORECASTING; MANUFACTURE; SEMICONDUCTOR DEVICE MANUFACTURE; COMPUTATIONAL COMPLEXITY; CRYSTAL DEFECTS; LIFE CYCLE; SEMICONDUCTOR DEVICE MODELS; SILICON WAFERS;

DEFECT CLUSTERING; LEARNING CURVES; MANUFACTURING YIELD; MODELING TECHNIQUE; POISSON YIELD MODELING; PROCESS COMPLEXITY; PRODUCT LIFE CYCLES; YIELD PREDICTION;

LIFE CYCLE; DYNAMIC RANDOM ACCESS STORAGE;

LEARNING CURVE EQUATIONS; POISSON YIELD MODEL;

EID: 0033328932     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSM.1999.808753     Document Type: Conference Paper

References (4)

1. [1 A. V. Ferns-Prabhu, "On llie Assumptions Contained in Semiconductor Yield Models, " IEEE Transactions On (Computer-Aided Design, vol. II, no. 8, pp. 966-975, Aug 1992
2. D. R. LaTourettc, "A Yield Learning Model for Integrated Circuit Manufacturing, " Semiconductor International, pp. 163 170, July 1995.
3. A. V. Fcrris-Prabliu, "A Cluster-Modified Poisson Model for Estimating Defect Density and Yield, " IEEE Transactions On Semiconductor Manufacturing, vol. 3, no. 2, pp. 54-59, May 1990.
4. |4] C. J. Tcplitz, The Learning Curve Deskbook: A Reference Guide to Theory, Calculations, and Applications, ch. 3, Quorum Books, 1991.