Optimized package test methodology for testing FRAM memories

Integrated Ferroelectrics

Volumn 26, Issue 1, 1999, Pages 297-310

  Mitra, Sanjay ^a   Humes, James ^a  

^a Ramtron International Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; FERROELECTRIC MATERIALS; QUALITY CONTROL; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE TESTING;

EXTENDED RETENTION TESTS; FERROELECTRIC SEMICONDUCTOR MEMORIES; PACKAGE TEST FLOW; SINGLE INSERTION TEST FLOW;

SEMICONDUCTOR STORAGE;

EID: 0033324633     PISSN: 10584587     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1080/10584589908215630     Document Type: Article

References (7)

1. Ramtron Specialty Memory Products Data Book, October 1996.
2. Test Methods and Procedures for Solid State Devices Used in Transportation /AutomotiveApplications, JEDEC Standard No. 22-B.
3. General Specification for Plastic Encapsulated Microcircuits for Use in Rugged Applications, JEDEC Standard No. 26.
4. MIL-STD-883D, Test Methods and Procedures for Microelectronics, 15 November 1991.
5. Ramtron controlled document 60-1001: Retention testing procedure.
6. Ramtron controlled document 60-1002: Endurance testing procedure.
7. Ramtron controlled document 60-5018: 16K Qualification report.