Low-power synapse/neuron cell for artificial neural networks

Microelectronics Journal

Volumn 30, Issue 12, 1999, Pages 1261-1264

  Lau, K T ^a   Lee, S T ^b   Chan, P K ^a  

^a Sch Elec Electron Eng   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MOSFET DEVICES; NEURAL NETWORKS;

RECONFIGURABLE LOW-VOLTAGE LOW-POWER CELLS; SYNAPSE/NEURAL CELLS;

VLSI CIRCUITS;

EID: 0033321778     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2692(99)00051-8     Document Type: Article

References (9)

1. R. Lippmann, An introduction to computing with neural nets, IEEE ASSP Mag., April (1987) 4-22.
2. Satyanarayana S., Tsividis Y.P., Graf H.P. A reconfigurable VLSI neural network. IEEE Journal of Solid-State Circuits. 27:(1):1992;67-81.
3. Salam F.A., Choi M.R. Analog MOS vector multipliers for the implementation of synapses in artificial neural networks. Journal of Circuits Systems and Computers. 1:(2):1991;205-228.
4. Pena-Finol J.S., Connelly J.A. A MOS four-quadrant analog multiplier using the quarter-square technique. IEEE Journal of Solid-State Circuits. 22:(6):1987;1064-1073.
5. Qin S.C., Geiger R.L. A ±5 V CMOS analog multiplier. IEEE Journal of Solid-State Circuits. 22:(6):1987;1143-1146.
6. Kim Y.H., Park S.B. Four-quadrant CMOS analogue multiplier. Electronics Letters. 28:(7):1992;649-650.
7. Liu S.I., Hwang Y.S. CMOS four-quadrant multiplier using bias feedback techniques. IEEE Journal of Solid-State Circuits. 29:(6):1994;750-752.
8. Lee S.T., Lau K.T. Low power building block for artificial neural networks. Electronics Letters. 31:(19):1995;1618-1619.
9. Choi J., Sheu B.J. VLSI design of compact and high-precision analog neural network processors. IJCNN. II:1992;637-641.