Marsh: min-area retiming with setup and hold constraints

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 2-6

  Sundararajan, Vijay ^a   Sapatnekar, Sachin S ^a   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); OPTIMIZATION; POLYNOMIALS; VLSI CIRCUITS;

HOLD CONSTRAINTS; POLYNOMIAL TIME ALGORITHM; RETIMING;

ALGORITHMS;

EID: 0033319365     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)