Observation of oxide breakdown and its effects on the characteristics of ultra-thin-oxide nMOSFET's

IEEE Electron Device Letters

Volumn 20, Issue 12, 1999, Pages 605-607

  Henson, W Kirklen ^a,b   Yang, Nian ^a   Wortman, Jimmie J ^a  

^a North Carolina State University   (United States)

^b IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC FILMS; ELECTRIC BREAKDOWN OF SOLIDS; OXIDES;

ELECTRIC FIELD DISTRIBUTIONS;

MOSFET DEVICES;

EID: 0033314798     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.806099     Document Type: Article

References (15)

1. H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S.-I. Nakamura, M. Saito, and H. Iwai, "1.5 nm direct-tunneling gate oxide Si MOSFET's," IEEE Trans. Electron Devices, vol. 43, p. 1233, Aug. 1996.
2. G. Timp, A. Agarwal, F. H. Baumann, T. Boone, M. Buonanno, R. Cirelli, V. Donnely, M. Foad, D. Grant, M. Green, H. Gossmann, S. Hillenius, J. Jackson, D. Jacobson, R. Kleinman, J. T.-C. Lee, W. Mansfield, S. Moccio, A. Murrell, M. O'Malley, J. Rosamilia, J. Sapjeta, P. Silverman, T. Sorch, W. W. Tai, D. Tennant, H. Vuong, and B. Weir, "Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFET's," in IEDM Tech. Dig., p. 930, 1997.
3. J. H. Stathis and D. J. DiMaria, "Reliability projection for ultra-thin oxides at low voltage," in IEDM Tech. Dig., p. 167, 1998.
4. D. J. Dumin, J. R. Maddux, R. S. Scott, and R. Subramoniam, "A model relating wearout to breakdown in thin oxides," IEEE Trans. Electron Devices, vol. 41, pp. 1570-1580, Sept. 1994.
5. 2 breakdown model for very low voltage lifetime extrapolation," IEEE Trans. Electron Devices, vol. 41, p. 761, May 1994.
6. D. J. DiMaria and J. H. Stathis, "Ultimate limit for defect generation in ultra-thin silicon dioxide," Appl. Phys. Lett., vol. 71, p. 3230, Dec. 1997.
7. G. Groeseneken, R. Degraeve, J. D. Blauwe, P. J. Roussel, M. Depas, and H. E. Maes, "On the breakdown statistics and mechanisms in ultrathin oxides and nitrided oxides," Electrochem. Proc., vol. 97-10, pp. 3-19, 1997.
8. 2 under long-term/low-field test conditions," in IEDM Tech. Dig., p. 171, 1998.
9. R. Degraeve, G. Groeseneken, R. Bellens, M. Depas, and H. E. Maes, "A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides," in IEDM Tech. Dig., pp. 863-866, 1995.
10. B. E. Weir, P. J. Silverman, D. Monroe, K. S. Krisch, M. A. Alam, G. B. Alers, T. W. Sorch, G. L. Timp, F. Baumann, C. T. Liu, Y. Ma, and D. Hwang, "Ultra-thin gate dielectrics: They break down, but do they fail?," in IEDM Tech. Dig., p. 73, 1997.
11. E. Wu, E. Nowak, J. Aitken, W. Abadeer, L. K. Han, and S. Lo, "Structural dependence of dielectric breakdown in ultra-thin gate oxides and its relationship to soft breakdown modes and device failure," in IEDM Tech. Dig., p. 187, 1998.
12. W. K. Henson, K. Z. Ahmed, E. M. Vogel, J. R. Hauser, J. J. Wortman, R. D. Venables, M. Xu, and D. Venables, "Estimating oxide thickness of tunnel oxides down to 1.4 nm with conventional capacitance-voltage measurements on MOS capacitors," IEEE Electron Device Lett., vol. 20, p. 179, Apr. 1999.
13. S.-I. Takagi, M. Takayanagi-Takagi, and A. Toriumi, "Accurate characterization of electron and hole inversion-layer capacitance and its impact on low voltage operation of scaled MOSFET's," in IEDM Tech. Dig., p. 619, 1998.
14. B. Cheng, M. Cao, P. Vande, W. Greene, H. Stork, Z. Yu, and J. C. S. Woo, "Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's," IEEE Trans. Electron Devices, vol. 46, pp. 261-262, Jan. 1999.
15. S. Thompson, P. Packan, T. Ghani, M. Stettler, M. Alavi, I. Post, S. Tyagi, S. Ahmed, S. Yang, and M. Bohr, "Source/Drain extension scaling for 0.1 μm and below channel length MOSFET's," Dig. Symp. VLSI Technol., p. 132, June 1998.