Novel Gate-Offset NAND Cell (GOC-NAND) technology suitable for high-density and low-voltage-operation flash memories

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1999, Pages 271-274

  Satoh, Shinji ^a   Nakamura, Takuya ^a   Shimizu, Kazuhiro ^a   Takeuchi, Ken ^a   Iizuka, Hirohisa ^a   Aritome, Seiichi ^a   Shirota, Riichiro ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; NAND CIRCUITS; THRESHOLD VOLTAGE;

ELECTRONICALLY ERASABLE PROM; FLASH MEMORIES; GATE OFFSET NAND CELL; PROGRAM DISTURBANCE;

PROM;

EID: 0033314628     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)