Reducing complexity of wafer flow to improve quality and throughput in a single-wafer cluster tool

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 1999, Pages 378-388

  Oh, Hilario L ^a  

^a Silicon Valley Group   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PROCESS ENGINEERING; QUALITY ASSURANCE; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS;

SINGLE-WAFER CLUSTER TOOL;

ELECTRONICS PACKAGING;

EID: 0033313732     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)