Self-consistent mosfet tunneling simulations-trends in the gate and substrate currents and the drain-current turnaround effect with oxide scaling

Materials Research Society Symposium - Proceedings

Volumn 567, Issue , 1999, Pages 227-239

  Massoud, H Z ^a   Shiely, J P ^a   Shanware, A ^a  

^a Duke University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; DIELECTRIC MATERIALS; ELECTRIC CURRENTS; ELECTRON TUNNELING; MATHEMATICAL MODELS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES;

COMPUTER SOFTWARE TUNNEL-PISCES; DEVICE GATE TUNNELING; DRAIN CURRENT TURNAROUND EFFECT; OXIDE SCALING; POLYSILICON GATE RESISTANCE; SELF CONSISTENT MOSFET TUNNELING SIMULATION;

MOSFET DEVICES;

EID: 0033312025     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1557/proc-567-227     Document Type: Article

References (7)

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6. G. Timp, et al, IEDM 1997.
7. A. Shanware et al, IEEE Electron Device Letters, submitted for publication.