Yield enhancement considerations for a single-chip multiprocessor system with embedded DRAM

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1999, Pages 31-39

  Rudack, Markus ^a   Niggemeyer, Dirk ^a  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CODES (SYMBOLS); COMPUTER SYSTEMS PROGRAMMING; DYNAMIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; ERROR CORRECTION; FAULT TOLERANT COMPUTER SYSTEMS; INTERFACES (COMPUTER); MACROS; MULTIPROCESSING SYSTEMS;

APPLICATION SPECIFIC INTERFACES; ERROR CORRECTION CODES (ECC); LARGE AREA INTEGRATED CIRCUITS (LAIC); PROGRAMMABLE SINGLE-CHIP MULTIPROCESSOR SYSTEMS; YIELD ENHANCEMENT;

MICROPROCESSOR CHIPS;

EID: 0033308925     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)