Predictive BSIM3v3 modeling for the 0.15-0.18 μm CMOS technology node: a process DOE based approach

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1999, Pages 353-356

  Vasanth, K ^a   Krick, J ^a   Unnikrishnan, S ^a   Nandakumar, M ^a   Jacobs, J ^a   Ehnis, P ^a   Green, K ^a   Machala, C ^a   Vrotsos, T ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; SCANNING ELECTRON MICROSCOPY; THRESHOLD VOLTAGE;

DESIGN OF EXPERIMENT APPROACH; SOFTWARE PACKAGE BSIM3V3;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0033307326     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)