High-throughput coherence controllers

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 1999, Pages 145-155

  Nanda, Ashwini K ^a   Nguyen, Anthony Trung ^a   Michael, Maged M ^a   Joseph, Douglas J ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; RESPONSE TIME (COMPUTER SYSTEMS);

DISTRIBUTED CACHE COHERENT SHARED MEMORY MULTIPROCESS; HIGH THROUGHPUT COHERENCE CONTROLLERS; MULTIPLE PROTOCOL ENGINES; PIPELINED PROTOCOL ENGINES; SPLIT REQUEST RESPONSE STREAMS;

MULTIPROCESSING SYSTEMS;

EID: 0033307067     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)