Decomposition of finite state machines for area, delay minimization

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1999, Pages 620-625

  Shelar, Rupesh S ^a   Desai, Madhav P ^a   Narayanan, H ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FUNCTIONS; LOGIC CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION; STATE ASSIGNMENT;

COST FUNCTIONS; DELAY MINIMIZATION; FINITE STATE MACHINES;

FINITE AUTOMATA;

EID: 0033300556     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (10)