Architectural synthesis of timed asynchronous systems

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1999, Pages 354-363

  Bachman, Brandon M ^a   Zheng, Hao ^a   Myers, Chris J ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; SHIFT REGISTERS;

DATA FLOW GRAPHS; HIGH-LEVEL SYNTHESIS CIRCUITS; TIMED ASYNCHRONOUS SYSTEMS;

VLSI CIRCUITS;

EID: 0033299132     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (18)