Architecture of the Atlas chip-multiprocessor: Dynamically parallelizing irregular applications

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1999, Pages 428-435

  Codrescu, Lucian ^a   Wills, D Scott ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; CORRELATION METHODS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; MULTIPROGRAMMING; PARALLEL PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS);

ATLAS CHIP-MULTIPROCESSORS; MULTISCALAR EXECUTION; SEQUENTIAL BINARIES;

VLSI CIRCUITS;

EID: 0033297669     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (27)