Design methodology for a one-shot Reed-Solomon encoder and decoder

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1999, Pages 60-67

  Morioka, Sumio ^a   Katayama, Yasunao ^a  

^a Tokyo Research Laboratories   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER ARCHITECTURE; DECODING; ENCODING (SYMBOLS); OPTIMIZATION; PARALLEL ALGORITHMS;

ONE-SHOT REED-SOLOMON ENCODER/DECODER;

ELECTRIC NETWORK SYNTHESIS;

EID: 0033296542     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (16)