Efficient implementation for high accuracy DCT processor based on FPGA

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 1999, Pages 508-511

  Naviner, L ^a   Danger, J L ^a   Laurent, C ^a   Garcia Garcia, A ^a  

^a TELECOM PARISTECH   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; COSINE TRANSFORMS; DISTRIBUTED PARAMETER NETWORKS; FIELD PROGRAMMABLE GATE ARRAYS; MATRIX ALGEBRA; SIGNAL ENCODING;

DISCRETE COSINE TRANSFORM PROCESSOR; DISTRIBUTED ARITHMETIC; ROW COLUMN DECOMPOSITION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033292558     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)