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Volumn 25, Issue 13, 1999, Pages 1635-1661

CP-PACS: A massively parallel processor at the University of Tsukuba

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; DATA STORAGE EQUIPMENT; MICROPROCESSOR CHIPS; RESPONSE TIME (COMPUTER SYSTEMS); VECTORS;

EID: 0033285365     PISSN: 01678191     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-8191(99)00078-2     Document Type: Article
Times cited : (13)

References (22)
  • 5
    • 0025539986 scopus 로고
    • Performance evaluation of the IBM RISC System/6000: Comparison of an optimized scalar processor with two vector processors
    • M.L. Simmons, H.J. Wasserman, Performance evaluation of the IBM RISC System/6000: comparison of an optimized scalar processor with two vector processors, in: Proceedings of Supercomputing'90, 1990, pp. 132-141.
    • (1990) Proceedings of Supercomputing'90 , pp. 132-141
    • Simmons, M.L.1    Wasserman, H.J.2
  • 11
    • 0003533609 scopus 로고    scopus 로고
    • Performance of various computers using standard linear equations software
    • University of Tennessee
    • J.J. Dongarra, Performance of various computers using standard linear equations software, Technical Report CS-89-85, University of Tennessee, 1996.
    • (1996) Technical Report CS-89-85
    • Dongarra, J.J.1
  • 12
    • 0343233078 scopus 로고    scopus 로고
    • Register allocation frameworks for slide-window architecture
    • in Japanese
    • T. Haraikawa, M. Soeno, Y. Yamashita, I. Nakata, Register allocation frameworks for slide-window architecture, Journal of IPSJ 39(9) (1998) 2684-2694 (in Japanese).
    • (1998) Journal of IPSJ , vol.39 , Issue.9 , pp. 2684-2694
    • Haraikawa, T.1    Soeno, M.2    Yamashita, Y.3    Nakata, I.4
  • 16
    • 0003015894 scopus 로고
    • Some scheduling techniques and easily schedulable horizontal architecture for high performance scientific computing
    • B.R. Rau, C.D. Glaeser, Some scheduling techniques and easily schedulable horizontal architecture for high performance scientific computing, in: Proceedings of the 14th Annual Workshop on Microprogramming, 1981, pp. 183-198.
    • (1981) Proceedings of the 14th Annual Workshop on Microprogramming , pp. 183-198
    • Rau, B.R.1    Glaeser, C.D.2
  • 17
    • 0002017307 scopus 로고
    • Instruction-level parallel processing: History, overview and perspective
    • B.R. Rau, J.A. Fisher, Instruction-level parallel processing: History, overview and perspective, J. Supercomputing 7 (1993) 9-50.
    • (1993) J. Supercomputing , vol.7 , pp. 9-50
    • Rau, B.R.1    Fisher, J.A.2
  • 18
  • 20
    • 33746152834 scopus 로고
    • Optimal software pipelining for loops with conditional branches
    • Information Processing Society of Japan, in Japanese
    • Y. Yamashita, I. Nakata, Optimal software pipelining for loops with conditional branches, in: Proceedings of the JSPP'94, Information Processing Society of Japan, 1994, pp. 17-24 (in Japanese).
    • (1994) Proceedings of the JSPP'94 , pp. 17-24
    • Yamashita, Y.1    Nakata, I.2
  • 22
    • 85031528794 scopus 로고    scopus 로고
    • http://www.top500.org/lists/1996/top500_9611.ps.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.