Development of supercomputers in Japan: Hardware and software

Parallel Computing

Volumn 25, Issue 13, 1999, Pages 1545-1567

  Oyanagi, Yoshio ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; PROGRAM COMPILERS; VECTORS;

VECTOR PROCESSING;

SUPERCOMPUTERS;

EID: 0033284536     PISSN: 01678191     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-8191(99)00084-8     Document Type: Article

References (72)

1. J.P. Riganati, P.B. Schneck, Supercomputing, IEEE Computer, October 1984, pp. 97-113.
2. O. Lubeck, J. Moore, R. Mendez, A benchmark comparison of three supercomputers: Fujitsu VP-200, Hitachi S810/20, and Cray X-MP/2, IEEE Computer, December 1985, pp. 10-24.
3. C.S. Ledbetter, A historical perspective of scientific computing in Japan and the United States, Supercomputing Review, November 1990, 31-37, December 1990, pp. 48-58.
4. S. Jarp, A review of Japan and Japanese high-end computers, CERN Technical Report CN/91/01, 1991.
5. R. Mendez, Japanese supercomputers: an overview, in: R. Mendez (Ed.), High Performance Computing Research and Practice in Japan, Wiley, New York, 1992, pp. 3-6.
6. N.P. Smith, Computing in Japan: from cocoon to competition, IEEE Computer, March 1997, pp. 26-33.
7. K. Uchida, Y. Seta, Y. Tanakura, The FACOM 230-75 array processor system, in: Proceedings of the Third USA-Japan Computer Conference 1978, pp. 369-373.
8. Y. Umetani, S. Kawabe, H. Horikoshi, T. Odaka, An analysis on applicability of the vector operation to scientific programs and the determination of an effective instruction repertoire, in: Proceedings of the Third USA-Japan Computer Conference, 1978, pp. 331-335.
9. S. Nagashima, Y. Inagami, T. Odaka, S. Kawabe, Design consideration for a high-speed vector processor: the Hitachi S-810, in: Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers ICCD'84, 1984, pp. 238-242.
10. T. Odaka, S. Nagashima, S. Kawabe, Hitachi Supercomputer S-810 array processor system, in: S. Fernbach (Ed.), Supercomputers Class VI Systems, Hardware and Software, North-Holland, Amsterdam, 1986, pp. 113-136.
11. H. Horikoshi, S. Nagashima, K. Furumaya, Supercomputer: Hitachi S-810, JARECT, vol. 18, in: T. Kitagawa (Ed.), Computer Science and Technologies, OHMSHA, LTD. and North-Holland, Amsterdam, 1988, pp. 57-69.
12. K. Miura, K. Uchida, FACOM vector processor VP-100/VP-200, in: J.S. Kowalik (Ed.), High Speed Computation, 1984, pp. 127-138.
13. K. Uchida, M. Itoh, High speed vector processors in Japan, Computer Physics Communications 37 (1985) 7-13.
14. K. Miura, Fujitsu's Supercomputer, FACOM vector processor system, in: S. Fernbach (Ed.), Supercomputers, Class VI Systems, Hardware and Software, North-Holland, Amsterdam, 1986, pp. 137-151.
15. K. Miura, Supercomputing in Japan, in: H.-J. Kugler (Ed.), Information Processing 86, pp. 557-564.
16. T. Watanabe, H. Katayama, A. Iwaya, Introduction of NEC supercomputer SX system, in: S. Fernbach (Ed.), Supercomputers, Class VI Systems, Hardware and Software, North-Holland, Amsterdam, 1986, pp. 153-167.
17. T. Watanabe, Design concept for highspeed vector and scalar processing: architecture of the NEC supercomputer SX system, Computer Design 1986, 1986, pp. 38-41.
18. T. Watanabe, Architecture and performance of NEC supercomputer SX system, Parallel Computing 5 (1/2) (1987) 247-255.
19. W. Nakayama, Japanese supercomputers in thermal perspective, in: R. Mendez (Ed.), High Performance Computing Research and Practice in Japan, Wiley, New York, 1992, pp. 55-73.
20. T. Odaka, S. Kawabe, H. Wada, Development of Hitachi supercomputer S-820 system, in: Proceedings of the Third International Conference on Supercomputing, Boston, 1988, pp. 71-77.
21. H. Wada, K. Ishii, M. Fukagawa, H. Murayama, S. Kawabe, high-speed processing schemes for summation type and iteration type vector instruction on Hitachi supercomputer S-820 system, in: Proceedings of the ACM International Conference on Supercomputing, Saint-Malo, 1988, pp. 197-206.
22. H. Wada, K. Ishii, S. Yazawa, S. Kawabe, High-speed vector instruction execution schemes of Hitachi supercomputer S-820 system, in: Proceedings of the International Conference on Parallel Processing, 1988, pp. 291-298.
23. H. Wada, S. Kawabe, T. Odaka, Hitachi supercomputer S-820 overview, in: Proceeding of Supercomputing Europe '89, vol. 1, 1989, pp. 139-147.
24. H. Wada, T. Isobe, M. Furukawa, S. Kawabe, High-speed storage control schemes of Hitachi supercomputer S-820 System, in: ACM International Conference on Supercomputing, Crete, Greece, 1989, pp. 341-350.
25. S. Kawabe, M. Hirai, S. Goto, Hitachi S-820 supercomputer system, in: R. Mendez (Ed.), High Performance Computing Research and Practice in Japan, Wiley, New York, 1992, pp. 35-53.
26. S. Kawabe, Hitachi S-820 supercomputer system, in: K. Fujii (Ed.), Supercomputers and Their Performance in Computational Fluid Dynamics, Vieweg, Braunschweig, 1993, pp. 43-61.
27. N. Uchida, M. Hirai, M. Yoshida, K. Hotta, Fujitsu VP2000 series, COMPCON Spring 90, 1990, pp. 4-11.
28. K. Miura, H. Nagakura, H. Tamura, VP2000 Series dual scalar and quadruple scalar models supercomputer systems, A new concept in vector processing, COMPCON Spring '91, 1991, pp. 294-302.
29. M. Takahashi, Y. Oinaga, K. Uchida, Fujitsu VP2000 series, in: R. Mendez (Ed.), High Performance Computing Research and Practice in Japan, Wiley, New York, 1992, pp. 7-20.
30. T. Watanabe, H. Matsumoto, P.D. Tannenbaum, Hardware technology and architecture of the NEC SX-3/SX-X supercomputer system, in: Proceedings of Supercomputing 89, 1989, pp. 842-846.
31. A. Iwaya, T. Watanabe, The parallel processing feature of the NEC SX-3 supercomputer system, International Journal of High Speed Computing 3 (3/4) 187-197.
32. T. Watanabe, The NEC SX-3 supercomputer system, COMPCON Spring 91, 1991, pp. 303-308.
33. T. Watanabe, A. Iwaya, The NEC SX-3 supercomputer series, in: R. Mendez (Ed.), High Performance Computing Research and Practice in Japan, Wiley, New York, 1992, pp. 21-33.
34. T. Watanabe, NEC SX-3 Supercomputer system, in: Kozo Fujii (Ed.), Supercomputers and their Performance in Computational Fluid Dynamics, pp. 63-75.
35. K. Ishii, H. Abe, S. Kawabe, M. Hirai, An overview of the Hitachi S-3800 series supercomputer, in: Proceedings of Supercomputing '92, 1992, pp. 65-81.
36. K. Kitai, T. Isobe, Y. Tanaka, Y. Tamaki, M. Fukagawa, T. Tanaka, Y. Inagami, Parallel processing architecture for the Hitachi S-3800 shared-memory vector multi-processor, in: Proceedings of International Conference on Supercomputing, 1993, pp. 288-297.
37. T. Sakakibara, K. Kitai, T. Isobe, S. Yazawa, T. Tanaka, Y. Inagami, Y. Tamaki, Scalable parallel memory architecture with a skew scheme, in: Proceedings of International Conference on Supercomputing, 1993, pp. 157-166.
38. K. Kitai, T. Isobe, T. Sakakibara, S. Yazawa, Y. Tamaki, T. Tanaka, K. Ishii, Distributed storage control unit for the Hitachi S-3800 multivector supercomputer, in: Proceedings of International Conference on Supercomputing, 1994, pp. 1-10.
39. T. Sakakibara, K. Kitai, T. Isobe, S. Yazawa, T. Tanaka, Y. Tamaki, Y. Inagami, Interprocessor memory access arbitrating scheme for TCMP type vector supercomputer, IEICE TRANS. INF. & SYST., E80-D (9)(1997) 925-932.
40. Y. Nakashima, T. Kitamura, H. Tamura, M. Takiuchi and K. Miura, Scalar Processor of the VPP500 parallel supercomputer, in: Proceedings of International Conference on Supercomputing, 1994, pp. 348-356.
41. T. Utsumi, M. Ikeda, M. Takamura, Architecture of the VPP500 parallel supercomputer, in: Proceedings of Supercomputing '94, 1994, pp. 478-487.
42. A. Nodomi, M. Ikeda, M. Takamura, K. Miura, Hardware performance of the VPP500 parallel supercomputer, in: J.J. Dongarra et al. (Eds.), High Performance Computing: Technology Method and Applications, 1995, pp. 103-120.
43. S.W. Hammond, R.D. Loft, P.D. Tannenbaum, Architecture and application: the performance of the NEC SX-4 on the NCAR Benchmark Suite, in: Proceedings of Supercomputing '96, 1996.
44. K. Kinoshita, Hardware system of the SX-series, NEC Research and Development 39 (4) (1998) 362-368.
45. K. Miura, Vector-parallel processing and Fujitsu's approach to high performance computing, VPP 300/VPP 700 Systems, in: Proceedings of the Fifth International School/Symposium for Space Simulations, 1997, pp. 448-450.
46. N. Uchida, Hardware of VX/VPP300/VPP700 series of vector-parallel supercomputer systems, Fujitsu Sci. Tech. J. 33 (1) (1997) 6-14.
47. Y. Koeda, Operating system of the VX/VPP300/VPP700 series of vector parallel supercomputer systems, Fujitsu Sci. Tech. J. 33 (1) (1997) 15-23.
48. K. Nakazawa, H. Nakamura, H. Imori, S. Kawabe, Pseudo vector processor based on register-windowed superscalar pipeline, in: Proceedings of Supercomputing '92, 1992, pp. 642-651.
49. K. Saito, M. Hashimoto, H. Sawamoto, R. Yamagata, T. Kumagai, E. Kamada, K. Matsubara, T. Isobe, T. Hotta, T. Nakano, T. Shimizu, K. Nakazawa, A 150 MHz superscalar RISC processor with pseudo vector processing feature, in: Proceedings Notebook for Hot Chips VII, 1995, pp. 197-205.
50. H. Fujii, Y. Yasuda, H. Akashi, Y. Inagami, M. Koga, O. Ishihara, M. Kashiyama, H. Wada, T. Sumimoto, Architecture and performance of the Hitachi SR2201 massively parallel processor system, in: Proceedings of the 11th International Parallel Processing Symposium, 1997, pp. 233-241.
51. Y. Yasuda, H. Fujii, H. Akashi, Y. Inagami, T. Tanaka, J. Nakagoshi, H. Wada, T. Sumimoto, Deadlock-free fault-tolerant routing in the multi-dimensional crossbar network and its implementation for the Hitachi SR2201, in: Proceedings of the 11th International Parallel Processing Symposium, 1997, pp. 346-352.
52. M. Shimasaki, On techniques in vectorizing compilers and optimizing program transformations for supercomputers, J. Information Processing 11 (1) (1987) 1-14.
53. H. Nobayashi, C. Eoyang, A comparison study of automatically vectorizing fortran compilers, in: R. Mendez (Ed.), High Performance Computing Research and Practice in Japan, Wiley, New York, 1992, pp. 115-128.
54. R. Takanuki, I. Nakata, Y. Umetani, Some compiling algorithms for array processor, in: Proceedings of the Third USA-Japan Computer Conference, 1978, pp. 273-279.
55. Y. Umetani, M. Yasumura, A vectorization algorithm for control statements, J. Information Processing 7 (3) (1984) 170-174.
56. M. Yasumura, Y. Tanaka, Y. Kanada, A. Aoyama, Compiling algorithms and techniques for the S-810 vector processor, in: Proceedings of the International Conference of Parallel Processing '84, 1984, pp. 285-290.
57. S. Gotou, Y. Tanaka, K. Iwasawa, Y. Kanada, A. Aoyama, Advanced vectorization techniques for supercomputers, J. Information Processing 11 (1) (1987) 22-31.
58. Yoshikazu Tanaka, Kyoko Iwasawa, Shizuo Gotou, Yukio Umetani, Compiling techniques for first-order linear recurrences on a vector computer, in: Proceedings of the Supercomputing '88, 1988, pp. 174-181.
59. Y. Tanaka, K. Iwasawa, Y. Umetani, S. Gotou, Compiling techniques for first-order linear recurrences on a vector computer, J. Supercomputing 4 (1990) 52-63.
60. C. Konno, M. Saji, N. Sagawa, Y. Umetani, Advanced implicit solution function of DEQSOL and its evaluation, in: Proceedings of the Fall Joint Computer Conference, Dallas, Texas, 1986, pp. 1026-1033.
61. Y. Umetani, M. Tsuji, K. Iwasawa, H. Hirayama, DEQSOL: a numerical simulation language for vector/parallel processors, in: Proceedings of IFIP WC2.5 Working Conference on Problem Solving Environments for Scientific Computing, Sophia Antipolis, 1987, pp. 147-164.
62. C. Konno, M. Yamabe, M. Saji, N. Sagawa, Y. Umetani, H. Hirayama, T. Ohta, Automatic code generation method of DEQSOL, J. Information Processing 11 (1) (1987) 15-21.
63. C. Konno, M. Yamabe, M. Saji, Y. Umetani, The BF (Boundary-Fitted) coordinate transformation technique of DEQSOL (Differential EQuation SOlver Language), Parallel Processing for Scientific Computing (SIAM), 1989, pp. 322-326.
64. C. Konno, Y. Umetani, M. Igai, T. Ohta, Interactive/Visual DEQSOL: interactive creation, debugging, diagnosis and visualization of numerical simulation, in: Mathematics and Computers in Simulation 31, North-Holland, Amsterdam, 1989, pp. 353-369.
65. Y. Umetani, C. Konno, T. Ohta, Visual PDEQSOL: a visual and interactive environment for numerical simulation, Proceedings of the IFIP TC2/WG2.5 Working Conference on Programming Environments for High-Level Scientific Problem Solving, September 1991, Karlsruhe Germany, North-Holland, Amsterdam, 1992.
66. S. Kamiya, F. Isobe, H. Takashima, M. Takiuchi, Practical vectorization techniques for the "FACOM VP", Information Processing 83 (1983) 389-394.
67. Y. Tanakura, S. Kamiya, K.-I. Hotta, Vector Fortran: compilers and optimizers, in: Raul Mendez (Ed.), High Performance Computing, Research and Practice in Japan, 1992, pp. 75-95.
68. E. Yamanaka, T. Shindo, Parallel language processing system for high-performance computing, Fujitsu Sci. Tech. J. 33 (1) (1997) 39-51.
69. H. Katayama, M. Tsukugoshi, FORTRAN and tuning utilities aiming at ease of use of a supercomputer, Fall Joint Computer Conference, 1986, pp. 1034-1039.
70. M. Tsukakoshi, H. Katayama, K. Abe, K. Yamamoto, The supercomputer SX system: fortran77/SX and support tools, in: Lana, Steven Kartashev (Eds.), in: Proceedings of the Second International Conference on Supercomputing, vol.1, 1987, pp. 72-79.
71. R. Hempel, H. Ritsdorf, F. Zimmermann, Efficient message passing interface implementations for nec parallel computers, NEC Research and Development 39 (4) (1998) 408-413.
72. Y. Hayashi, S. Sakon, Y. Seo, K. Suehiro, M. Tamura, H. Murai, parallelization in an HPF language processor, NEC Research and Development 39 (4) (1998) 414-421.