Novel backside sample preparation processes for advanced CMOS integrated circuits failure analysis

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 1999, Pages 119-122

  Chew, Y Y ^a   Siek, K H ^a   Yee, W M ^a  

^a Intel Technology Malaysia Sdn Bhd   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

ANTIREFLECTION COATINGS; ELECTRONICS PACKAGING; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; LIGHT EMISSION; OPTICAL MICROSCOPY; POLISHING; SILICON WAFERS;

PHOTOEMISSION MICROSCOPY;

CMOS INTEGRATED CIRCUITS;

EID: 0033284103     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ipfa.1999.791318     Document Type: Conference Paper

References (2)